A programmable multistage half-band FIR decimator for input datarates up to 2.56 MSPS

A multistage half-band finite-impulse response (FIR) decimator is developed. It is implemented using a 40000-gate 1.5-μ CMOS gate array, which dissipates 1.5 W at a clock rate of 25.6 MHz (a sampling rate of 2.56 MHz). Its power-of-two decimation ratio is programmable within the range 1 through 2¹⁷ for frequency zooming in fast Fourier transform (FFT) spectrum analysis, and it is preceded by a digital multiplier for frequency shifting. The filter handles 20-b 2.56-megasamples/s (MSPS) input data. The frequency resolution is increased by up to 2¹⁷ times without aliasing resulting in frequency resolution on the order of 20 mHz. The decimator has a 96-dB dynamic range