A 63-mW H.264/MPEG-4 audio/visual codec LSI with module-wise dynamic Voltage/frequency scaling |
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| Authors: | Fujiyoshi T Shiratake S Nomura S Nishikawa T Kitasho Y Arakida H Okuda Y Tsuboi Y Hamada M Hara H Fujita T Hatori F Shimazawa T Yahagi K Takeda H Murakata M Minami F Kawabe N Kitahara T Seta K Takahashi M Oowaki Y Furuyama T |
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| Affiliation: | Toshiba Corp., Kawasaki, Japan; |
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| Abstract: | A single-chip H.264 and MPEG-4 audio-visual LSI for mobile applications including terrestrial digital broadcasting system (ISDB-T / DVB-H) with a module-wise, dynamic voltage/frequency scaling architecture is presented for the first time. This LSI can keep operating even during the voltage/frequency transition, so there is no performance overhead. It is realized through a dynamic deskewing system and an on-chip voltage regulator with slew rate control. By the combination with traditional low power techniques such as embedded DRAM and clock gating, it consumes only 63 mW in decoding QVGA H.264 video at 15 frames/sec and MPEG-4 AAC LC audio simultaneously. |
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