Robust FinFET SRAM design based on dynamic back-gate voltage adjustment |
| |
| Affiliation: | 1. Nanoelectronics Center of Excellence, School of Electrical and Computer Engineering, College of Engineering, University of Tehran, Tehran, Iran;2. Department of Electrical and Computer Engineering, San Francisco State University, CA, USA;1. Department of Electrical and Computer Engineering, University of Maryland, College Park, MD 20742, USA;2. Freescale Semiconductor, 2100 East Elliot Road, Tempe, AZ 85284, USA;3. Qualcomm Inc., 5775 Morehouse Drive, San Diego, CA 92121, USA;1. Moscow Engineering Physics Institute (NRNU “MEPhI”), Moscow, Russia;2. Centro Nacional de Microelectrónica (CNM, CSIC), Barcelona, Spain;3. Santa Cruz Institute for Particle Physics (SCIPP, UCSC), Santa Cruz, CA, USA;4. Lawrence Berkeley National Laboratory (LBNL), Physics Division, Berkeley, CA, USA;5. Brookhaven National Laboratory (BNL), Upton, NY, USA;6. University of Pennsylvania, Philadelphia, PA, USA;1. Politecnico di Torino, Dipartimento di Automatica e Informatica, Torino, Italy;2. Universidade Federal do Rio Grande do Sul (UFRGS), Porto Alegre, Brazil;1. Aselsan, Mehmet Akif Ersoy Mahallesi 296, 16, 06370 Yenimahalle, Ankara, Turkey;2. Universidad Antonio de Nebrija, C/Pirineos, 55 E-28040 Madrid, Spain |
| |
| Abstract: | In this paper, we propose a robust SRAM design which is based on FinFETs. The design is performed by dynamically adjusting the back-gate voltages of pull-up transistors. For the write operation, we use an extra write driver which sets the desired back-gate voltages during this operation. This approach considerably increases the write margin. During the hold state, the back-gates are precharged to the supply voltage using an extra precharge circuit. This decreases the static power. Finally, we use nMOS switches to provide the optimum back-gate voltages during the read state. To minimize the area and power overheads, an instance of the circuitry is used for each column. The performance of the proposed technique is assessed using mixed mode device/circuit simulations for a physical gate length of 22 nm. The results show that the minimum operating voltage for six-sigma read and write yield is about 0.15 V lower than that of the recently proposed structures. In addition, the suggested SRAM shows significantly higher write margin and lower static power compared to the recently proposed structures. The minimum operating voltage of our proposed structure can be lowered down to 0.5 V through some work function tuning to balance the read and write stability. This minimum voltage is 0.1 V lower than the minimum operating voltage of the other structures with similar work function tunings. |
| |
| Keywords: | SRAM Dynamic back-gate design FinFET Robust Low power |
| 本文献已被 ScienceDirect 等数据库收录！ |
|
