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Study of the UBM to copper interface robustness of solder bumps in flip chip packages
Affiliation:1. STMicroelectronics, 850, rue Jean Monnet, 38926 Crolles Cedex, France;2. Laboratory of Computer Sciences, Paris 6 (LIP6), Systems On Chips Department, UPMC University, 4 place Jussieu, 75252 Paris Cedex 05, France;1. Engineering Product Development Pillar, Singapore University of Technology and Design, Singapore 138 682, Singapore;2. Department of Mechanical Engineering, Massachusetts Institute of Technology, Cambridge, MA 02139, USA;1. SAGE-ENISo, National Engineering School of Sousse, 4023 University of Sousse, Tunisia;2. Al Leith Engineering College, Umm Al-Qura University, Saudi Arabia;3. ISIM, University of Gabes, 6072 Gabes, Tunisia;4. ESTACA Research Center, 92532 Levallois Perret, Paris, France;5. GPM-UMR CNRS 6634, University of Rouen, 76801 Saint Etienne du Rouvray, France;1. Le2i, UMR CNRS 6306, University of Burgundy, 9 Avenue Alain Savary, 21000 Dijon, France;2. Centre National d’Etudes Spatiales (CNES), 18 Avenue Edouard Belin, 31401 Toulouse, France;1. Departament d’Enginyeria Electrònica, Universitat Autònoma de Barcelona, Cerdanyola del Valles, Spain;2. Departamento de Electricidad y Electrónica, Universidad de Valladolid, Valladolid, Spain;3. Department of Chemistry, University of Helsinki, Helsinki, Finland;1. University of Vienna, Physics of Nanostructured Materials, Vienna, Austria;2. Materials Center Leoben Forschung GmbH, Leoben, Austria;3. Vienna University of Technology, Faculty of Technical Chemistry, Vienna, Austria
Abstract:Shear tests on SnAg solder bumps were performed with a reduced height to the surface for a high shear force on the under bump metallurgy (UBM) to redistribution layer (RDL) copper interface. By this the failure mechanism of UBM–RDL delamination after stress tests simulating several assembly reflows could be reproduced. A design of experiment was done with corner wafers at worst case conditions for topography and interface clean. TEM cross sections confirmed nano scale carbon residues in the interface when reducing the clean efficiency. This results in a mechanically weakened interface with a present electrical contact. The shear test with reduced height is a more severe test beyond the JEDEC test to verify the bump robustness. This is important when existing bump technologies are used for flip chip package solutions with increased solder reflow requirements.
Keywords:Flip chip  Bump  Shear test  Robustness  UBM delamination  TEM
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