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Reliability of Wafer Level Chip Scale Packages
Affiliation:1. NXP Semiconductors, Gerstweg 2, 6534AE Nijmegen, The Netherlands;2. Information Technology Laboratory, Leibniz Universität Hannover, Schneiderberg 32, 30167 Hannover, Germany;1. Engineering Product Development Pillar, Singapore University of Technology and Design, Singapore 138 682, Singapore;2. Department of Mechanical Engineering, Massachusetts Institute of Technology, Cambridge, MA 02139, USA;1. STMicroelectronics, 850, rue Jean Monnet, 38926 Crolles Cedex, France;2. Laboratory of Computer Sciences, Paris 6 (LIP6), Systems On Chips Department, UPMC University, 4 place Jussieu, 75252 Paris Cedex 05, France;1. Department of Industrial Engineering DIIn, University of Salerno, Via Giovanni Paolo II 132, 84084 Fisciano, SA, Italy;2. Faculty of Mathematics and Computer Science, FernUniversität Hagen, 58084 Hagen, Germany;1. Departament d’Enginyeria Electrònica, Universitat Autònoma de Barcelona, Cerdanyola del Valles, Spain;2. Departamento de Electricidad y Electrónica, Universidad de Valladolid, Valladolid, Spain;3. Department of Chemistry, University of Helsinki, Helsinki, Finland;1. Le2i, UMR CNRS 6306, University of Burgundy, 9 Avenue Alain Savary, 21000 Dijon, France;2. Centre National d’Etudes Spatiales (CNES), 18 Avenue Edouard Belin, 31401 Toulouse, France
Abstract:
Keywords:Wafer Level Chip Scale Package  Passivation cracks  Electromigration  Finite Element Modeling  Mission profile  Life time prediction
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