Design and verification of a frequency domain equalizer |
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| Affiliation: | 1. Department of Electrical and Computer Engineering, Concordia University, Montreal, Quebec, Canada H3G 1M8;2. Department of Electrical and Computer Engineering, Khalifa University of Science, Technology and Research, P.O. Box 573 Sharjah, United Arab Emirates;3. École Nationale d''ingénieurs de Sousse, Sousse, Tunisia;1. Department of Electronic Engineering, Jinwen University of Science and Technology, No. 99, Anzhong Road, Xindian Dist., New Taipei City 23154, Taiwan;2. Instrument Technology Research Center, National Applied Research Laboratories, No. 20, R&D Road VI, Hsinchu Science Park, Hsinchu 30076, Taiwan;1. LIRMM - UM2/CNRS, 161 rue Ada, 34095, Montpellier cedex 5, France;2. ESYCOM, ESIEE Paris, Université Paris-Est, F-93162 Noisy-le-Grand, France;3. CEA, DAM, DIF, F-91297 Arpajon, France;1. HP R&D, Porto Alegre, Brazil;2. PUCRS, Faculty of Informatics, Porto Alegre, Brazil |
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| Abstract: | In this work we provide a methodology for the design and verification of a frequency domain equalizer. The performance analysis of the equalizer is conducted using two methods: simulation based verification in Simulink and System Generator and theorem proving techniques in Higher Order Logic. We conduct both floating-point and fixed-point error estimations for the design in Simulink and System Generator, respectively. Then, we use formal error analysis based on the theorem proving to verify an implementation of the frequency domain equalizer based on the Fast LMS algorithm. The formal error analysis and simulation based error estimation of the algorithm intend to show that, when converting from one number domain to another, the algorithm produces the same values with an accepted error margin caused by the round-off error accumulation. This work shows the efficiency of combining simulation and formal verification based methods in verifying complex systems such as the frequency domain equalizer. |
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| Keywords: | Error analysis Theorem proving Design and verification |
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