A comparative study of energy/power consumption in parallel decimal multipliers |
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| Affiliation: | 1. Sharif University of Technology, Computer Engineering, Embedded Systems Research Laboratory (ESRLab), Azadi Ave, Tehran, Iran;2. Institute for Research in Fundamental Sciences (IPM), School of Computer Science, Iran;1. University ENT Department, Medical School of Comenius University and University Hospital Bratislava, Slovakia;2. ENT Department, University Hospitals Coventry and Warwickshire, University of Warwick, United Kingdom;3. ENT Department, Faculty Hospital Trenčín, Slovakia;4. Histopatológia a.s., Bratislava, Slovakia;5. Department of Pneumology and Phtiseology, Medical School of Comenius University and University Hospital Bratislava, Slovakia;6. ENT Department, Alexandra Hospital, Singapore;7. Department of Otolaryngology, University Hospital Ostrava, Czech Republic;1. Department of Electronic Engineering, City University of Hong Kong, Hong Kong SAR;2. Center for Neural Engineering, Department of Biomedical Engineering, University of Southern California, Los Angeles, CA 90089, USA |
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| Abstract: | Decimal multiplication is a frequent operation with inherent complexity in implementation. Commercial and financial applications require working with decimal numbers while it has been shown that if we convert decimal number to binary ones, this will negatively influence the preciseness required for these applications. Existing research works on parallel decimal multipliers have mainly focused on latency and area as two major factors to be improved. However, energy/power consumption is another prominent issue in today׳s digital systems. While the energy consumption of parallel decimal multipliers has not been addressed in previous works, in this paper we present a comparative study of parallel decimal multipliers, considering energy/power consumption, leakage and dynamic power consumption, beside latency and area. This study can provide some guidelines for EDA tools and hardware designers to choose proper multiplier based on given applications and design constraints. All designs in were implemented using VHDL and synthesized in Design-Compiler toolbox with TSMC 45 nm technology file. |
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| Keywords: | Decimal multiplication Parallel multiplier Energy consumption Power consumption |
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