Graphene nanoribbon crossbar architecture for low power and dense circuit implementations |
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| Affiliation: | 1. Department of Electrical and Computer Engineering, Babol University of Technology, Babol, Iran;2. Advanced VLSI Lab., School of Electrical and Computer Engineering, College of Engineering, University of Tehran, Tehran 14395-515, Iran;1. Complutense University of Madrid, Computer Architecture and Automation, Facultad de Informática, c/Prof. García Santesmases s/n, 28040 Madrid, Madrid, Spain;2. Northwestern University of Evanston, Department of Electrical Engineering and Computer Science, Tech Building, L471, 2145 Sheridan Road, 60208 Evanston (IL), United States;1. State Key Laboratory of Coal Resources and Safe Mining, China University of Mining and Technology, Beijing 100083, China;2. School of Mechanical Electronic & Information Engineering, China University of Mining and Technology, Beijing 100083, China;1. Institute of Nanotechnology, Karlsruhe Institute of Technology, P.O. Box 3640, 76021 Karlsruhe, Germany;2. Nanjing University of Science and Technology, Herbert Gleiter Institute of Nanoscience, Building 340, Nanjing, Jiangsu 2 10094, PR China |
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| Abstract: | Crossbar array is a promising nanoscale architecture which can be used for logic circuit implementation. In this work, a graphene nanoribbon (GNR) based crossbar architecture is proposed. This design uses parallel GNRs as device channel and metal as gate, source and drain contacts. Schottky-barrier type graphene nanoribbon field-effect transistors (SB-GNRFETs) are formed at the cross points of the GNRs and the metallic gates. Benchmark circuits are implemented using the proposed crossbar, Si-CMOS and multi-gate Si-CMOS approaches to evaluate the performance of the crossbar architecture compared to the conventional CMOS logic design. The compact SPICE model of SB-GNRFET was used to simulate crossbar-based circuits. The CMOS circuits are also simulated using 16 nm technology parameters. Simulation results of benchmark circuits using SIS synthesis tool indicate that the GNR-based crossbar circuits outperform conventional CMOS circuits in low power applications. Area optimized cell libraries are implemented based on the asymmetric crossbar architecture. The area of the circuit can be more reduced using this architecture at the expense of higher delay. The crossbar cells can be combined with CMOS cells to exhibit better performance in terms of EDP. |
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| Keywords: | Crossbar array architectures Graphene nanoribbon FET (GNRFET) Nanoelectronic |
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