速度优化再分解设计方法

在超大规模集成电路的设计过程中,库单元绑定是非常重要的一环。它的目标是：通过特定的方法,把一组布尔网络表述的逻辑功能用具体的库单元实现。逻辑分解是这一过程中非常重要的一步,经分解产生的主题图质量的好坏直接影响到最后的设计结果。针对主题图中的延时问题,提出了“再分解”这一新设计方法。该方法采用“逻辑变换”技术,使主题图中从基本输入到基本输出的各条线路延时的差距尽是缩小,从而达到减小整个主题图延时的目的。

Design Approach of Redecomposition for Speed Optimization

Cell library binding is a very important step during the design of VLSI.The purpose of cell library binding is to implement the logic functions of a group of Boolean networks by using some library cells.Logic decomposition is significant during the process.The subject graph, which is obtained by logic decomposition directly, affects the final result of the design.In this paper, a new method named "logic redecomposition" is presented, which aims at the delay of the subject graph.Logic transformation technology is used in this method to reduce the difference of the delay of each path from primary input to primary output, thus decreasing the delay of the whole subject graph