Methods of measuring the size and complexity of PLC programs in different logic control design methodologies

Currently there is a wide variety of logic control design methodologies used in industrial logic design. These methodologies include ladder diagrams, function block diagrams, sequential function charts, and flow charts, but driven by a desire for verifiability, academics are developing additional logic control design methodologies, such as modular finite state machines and Petri nets. Using these, important properties of programs can be verified and some logic can be generated automatically from a part plan. The main contribution of this paper is to define methods for measuring programs written in different methodologies, so that the performance of the methodologies can be compared.We demonstrate these methods of measurement using four program samples that perform similar functions on the same machine, written in four logic control design methodologies: ladder diagrams, Petri nets, signal interpreted Petri nets and modular finite state machines.