基于钟控传输门绝热逻辑电路的绝热FIFO设计

通过研究先进先出存储堆栈(FIFO)和钟控传输门绝热逻辑(CTGAL)电路工作原理及结构，提出了基于CTGAL电路的绝热FIFO设计方案.该方案运用绝热计算原理，基于晶体管级设计电路,有效避免了传统CMOS逻辑的FIFO必然遇到的亚稳态和异步信号处理等难题，实现了深度为16的基于CTGAL电路的绝热FIFO结构.HSPICE模拟结果表明，所设计的电路具有正确的逻辑功能，与基于有效电荷恢复逻辑（ECRL）的绝热FIFO相比较，电路平均功耗节省达71%.

Design of adiabatic FIFO based on clocked transmission gate adiabatic logic circuit

The working principle and structure of first in first out(FIFO) and clocked transmission gate adiabatic logic(CTGAL) were investigated,and a design scheme of adiabatic FIFO based on CTGAL was proposed.The design scheme considers the circuit structure in transistor level by using the principle of adiabatic computing,which can effectively avoid the inevitable problems of metastability and asynchronism signals treatments in FIFO based on conventional complementary metal oxide semiconductor(CMOS) logic.A 16-depth adiabatic FIFO based on CTGAL was achieved.HSPICE simulation verified the valid functionality of the designed circuit,and showed that the proposed circuit could attain energy saving of 71%,compared to the adiabatic FIFO based on efficient charge recovery logic(ECRL).