用于CMOS低中频GPS接收机的模数转换器的设计考虑与实现

首先对用于CMOS低中频GPS接收机的模数转换器(ADC)进行了设计考虑.由ADC引入的信噪比降低与四个因素有关:中频带宽,采样率,ADC的比特数及ADC的最大阈值与噪声均方根比值.在设计考虑的基础上,采用TSMC 0.25tan CMOS单层多晶硅五层金属工艺实现了一个4 bit 16.368 MHz闪烁型模数转换器,并将重点放在了前置放大器和提出的新的比较器的设计和优化上.在时钟采样率16.368 MHz和输入信号频率4.092 MHz的条件下,转换器测试得到的信噪失真比为24.7 dB,无杂散动态范围为32.1 dB,积分非线性为 0.31/-0.46LSB,差分非线性为 0.66/-0.46LSB,功耗为3.5mW.ADC占用芯片面积0.07 mm2.

Design Considerations and Implementation of an Analog-to-Digital Converter for a CMOS Low-IF GPS Receiver

The design considerations of an analog-to-digital converter (ADC) for a CMOS Low-IF GPS re- ceiver are described first. Signal-to-noise degradation due to ADC is dependent on four factors: the IF bandwidth, the sampling rate, the number of bits of the ADC, and the ratio of the maximum ADC thresh-old to the root-mean-square noise level. Then based on the design considerations, a 4 bit 16. 368 MHz Flash ADC is implemented using TSMC 0. 25/μm CMOS single-poly five-metal process and the special at-tention is spent on the design and optimization of the preamplifier and proposed new comparator. The con-verter achieves a peak signal-to-noise-and-distortion ratio of 24.7 dB, peak spurious-free dynamic range of 32.1 dB, integral nonlinearity of +0. 31/-0. 46LSB, integral nonlinearity of +0.66/-0.46LSB, and a pow-er of 3.5 mW at 16.368 MHz clock and fin=4. 092 MHz. The converter occupies 0.07 mm2 of chip area.