具有加长LDD结构的高压CMOS器件

基于中国科学院微电子研究所的0.8μm标准N阱CMOS工艺以及ISETCAD软件,模拟了具有加长LDD结构的高压CMOS器件.器件的击穿电压可以达到30V以上.加长的LDD结构是通过非自对准的源漏注入实现的.LDD区域的长度和该区域的掺杂浓度对器件击穿影响很大.对于不同的工作电压(10-20 V),实验给出了相应的LDD区域长度和该区域的注入剂量.只需要在标准工艺的基础上增加三层掩模版和相应的工艺步骤就能实现低高压工艺的兼容.而且对称结构和非对称结构(具有更大的驱动电流)器件都能实现.与LDMOS或DDDMOS工艺相比,节省了成本,而且所设计的高压器件尺寸较小,有利于集成.

High voltage CMOS devices with lengthened LDD structures

Based on 0.8 μm standard N - well CMOS process belonging to IMECAS ( Institute of Microelectronics of Chinese Academy of Sciences) and the software ISETCAD, high voltage (HV) CMOS devices with lengthened LDD region were simulated. The breakdown voltages of these devices have reached more than 30V. The lengthened LDD structure was implemented by the non - self - aligned source/drain implantation. And the length of LDD region and the impurity concentration of this region affect the devices breakdown voltage greatly. For different supply voltages 10 -20V, different LDD region length and LDD implantation dose have been obtained. These HV devices can be easily integrated with conventional ones with only three more masks and several added process steps. Symmetric and asymmetric (having larger driving current) devices both can be implemented. Compared with LDMOS or DDDMOS process more costs can be saved. And the device size is also smaller than that of LDMOS and DDDMOS device.