一种双采样6 bit 150MSPS CMOS折叠内插式ADC。

CMOS折叠预处理电路的带宽和失调是限制折叠内插式ADC的动态和静态特性的主要原因之一。所设计的ADC采用一种双采样保持电路降低了对折叠器的带宽要求,获得了优良的动态特性;提出一种改进结构的全平衡折叠电路,降低了折叠器本身的失调,同时改善了ADC的静态和动态特性。仿真结果表明:在输入信号频率74.1MHz、采样频率150M时SNDR为37.2dB;INL、DNL分别为0.5/0.6LSB。芯片采用1stSilicon0.25μmCMOS工艺流片,并用于10/100Base-TPHY芯片中,测试结果表明,该ADC能正常工作,功耗为135mW,芯片有效面积0.4mm2。

A Double-sampling 6 bit 150 MSPS CMOS Folding and Interpolating ADC

Bandwidth and offset of CMOS folding preprocessing circuit are the main factors, which limit the dynamic and static characteristics of folding-interpolating ADC. This paper proposes an ADC, which adopts a double-sampling circuit to minimize the bandwidth requirement of the folder and achieves good dynamic characteristics. It also proposes an improved full-balanced folder, which minimizes its offset and improves the ADC's static and dynamic characteristics. This ADC uses 3.3 V supply. The simulated results using 1st Silicon 0.25 μm CMOS technology, BSIM3V3 model and spectre simulator are as below:DNL/INL is 0.5/0.6LSB, SNDR with 74.1 M input, 150 M sampling rate is 37.2 dB. The total power consumption is 135 mW and the chip area is 0.4 mm~2.