基于FPGA的IEEE802.16e标准LDPC编码器设计

针对通信过程中突发信道造成的集中错码现象,并且兼顾编码器的时效性要求,设计了一种 IEEE 802.16e 标准下码长 576,码率 1/2 的 LDPC 码硬件编码器,通过 Verilog 语言进行描述,采用并行结构设计和模型矩阵元素预存的方式降低了资源占用量,提高了工作速度,通过仿真、综合与实现结果验证了方案的有效性。

IEEE 802.16e Standard LDPC Encoder Design Based on FPGA

Aiming at the phenomenon of concentrated error code caused by burst channel in communication process, and considering the timeliness of encode, a LDPC code hardware encoder with length of 576 and bit rate of 1/2 in IEEE 802.16e standard is designed, which is described by Verilog, adopts parallel structure design and element prestorage to reduce the resource consumption, and increased working rate, the efficiency of the scheme is verified by simulation and synthesis and implementation results.