A 5-V-only operation 0.6-μm flash EEPROM with row decoder schemein triple-well structure |
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| Authors: | Umezawa A. Atsumi S. Kuriyama M. Banba H. Imamiya K. Naruke K. Yamada S. Obi E. Oshikiri M. Suzuki T. Tanaka S. |
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| Affiliation: | Toshiba Corp., Kawasaki; |
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| Abstract: | An experimental 4-Mb flash EEPROM has been developed based on 0.6-μm triple-well CMOS technology in order to establish circuit technology for high-density flash memories. A cell size of 2.0×1.8 μm2 has been achieved by using a negative-gate-biased source erase scheme and a self-aligned source (SAS) process technology. A newly developed row decoder with a triple-well structure has been realized in accordance with its small cell size. The source voltage during the erase operation was reduced by applying a negative voltage to the word line, which results in a 5-V-only operation. The chip size of the 4-Mb flash EEPROM is 8.11×6.95 mm2, and the estimated chip size of a 16-Mb flash EEPROM is 98.4 mm2 by using the minimal cell size (2.0×10 μm2) |
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