MOS C-V characterization of ultrathin gate oxide thickness (1.3-1.8nm) |
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Authors: | Chang-Hoon Choi Jung-Suk Goo Tae-Young Oh Zhiping Yu Dutton R.W. Bayoumi A. Min Cao Voorde P.V. Vook D. Diaz C.H. |
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Affiliation: | Center for Integrated Syst., Stanford Univ., CA ; |
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Abstract: | An equivalent circuit approach to MOS capacitance-voltage (C-V) modeling of ultrathin gate oxides (1.3-1.8 nm) is proposed. Capacitance simulation including polysilicon depletion is based on quantum mechanical (QM) corrections implemented in a two-dimensional (2-D) device simulator; tunneling current is calculated using a one-dimensional (1-D) Green's function solver. The sharp decrease in capacitance observed for gate oxides below 2.0 nm in both accumulation and inversion is modeled using distributed voltage-controlled RC networks. The imaginary components of small-signal input admittance obtained from AC network analysis agree well with measured capacitance |
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