Assertion Based Verification and Analysis of Network Processor Architectures期刊界 All Journals 搜尽天下杂志传播学术成果专业期刊搜索期刊信息化学术搜索

Assertion Based Verification and Analysis of Network Processor Architectures

Authors:	Xi?Chen author-information" > author-information__contact u-icon-before" > mailto:xichen@cs.ucr.edu" title=" xichen@cs.ucr.edu" itemprop=" email" data-track=" click" data-track-action=" Email author" data-track-label=" " >Email author,Yan?Luo,Harry?Hsieh,Laxmi?Bhuyan,Felice?Balarin

Affiliation:	(1) Department of Computer Science, University of California, Riverside, CA, 92521;(2) Cadence Berkeley Laboratories, Berkeley, CA, 94704

Abstract:

Keywords:	assertion verification network processor logic of constraints
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