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Automated Design of Combinational Logic Circuits Using the Ant System |
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| Authors: | Carlos A. Coello Coello Rosa Laura Zavala Gutiérrez Benito Mendoza García Arturo Hernández Aguirre |
| Affiliation: | 1. Depto. de Ingeniería Eléctrica Sección de Computación , CINVESTAV-IPN , Av. Instituto Politécnico Nacional No. 2508 Col. San Pedro Zacatenco, México, D. F., 07300, Mexico E-mail: ceollo@cs.cinvesta.mx;2. MIA , LANIA-UV , Sebastia′n Camacho 5, Xalapa, Veracruz, 91090, Mexico;3. EECS Department , Tulane University , New Orleans, LA, 70118, USA |
| Abstract: | This paper proposes an application of the Ant System (AS) to optimize combinational logic circuits at the gate level. A measure of quality improvement is defined in partially built circuits to compute the distances required by the AS, and those solutions that represent functional circuits with a minimum number of gates are considered as optimal. The proposed methodology is described together with some examples taken from the literature that illustrate the feasibility of the approach. |
| Keywords: | Circuit Design Ant Colony System Evolvable Hardware Circuit Optimization |