A 5-GHz programmable frequency divider in 0.18-μm CMOS technology |
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作者姓名: | 舒海涌 李智群 |
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作者单位: | [1]Institute of RF- & OE-ICs, Southeast University, Nanjing 210096, China [2]Engineering Research Center of RF-ICs & RF-Systems, Ministry of Education, Southeast University, Nanjing 210096, China |
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基金项目: | supported by the National High Technology Research and Development Program of China(No.2007AA01Z2A7); the Science and Technology Program of Zhejiang Province China(No.2008C16017). |
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摘 要: | 正A 5-GHz CMOS programmable frequency divider whose modulus can be varied from 2403 to 2480 for 2.4-GHz ZigBee applications is presented.The divider based on a dual-modulus prescaler(DMP) and pulse-swallow counter is designed to reduce power consumption and chip area.Implemented in the 0.18-μm mixed-signal CMOS process,the divider operates over a wide range of 1-7.4 GHz with an input signal of 7.5 dBm;the programmable divider output phase noise is -125.3 dBc/Hz at an offset of 100 kHz.The core circuit without test buffer consumes 4.3 mA current from a 1.8 V power supply and occupies a chip area of approximately 0.015 mm~2.The experimental results indicate that the programmable divider works well for its application in frequency synthesizers.
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关 键 词: | 可编程分频器 CMOS技术 千兆赫 微米 ZigBee CMOS工艺 芯片面积 预置分频器 |
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