带有自适应频率校准单元的26~41 GHz锁相环

采用45 nm SOI CMOS工艺,设计了一种带有自适应频率校准单元的26~41 GHz 锁相环。该锁相环包括输入缓冲器、鉴频鉴相器、电荷泵、环路滤波器、压控振荡器、高速时钟选通器、分频器和频率数字校准单元。采用了基于双LC-VCO的整数分频锁相环,使用了自适应频率选择的数字校准算法,使得锁相环能在不同参考时钟下自适应地调整工作频率范围。仿真结果表明,该锁相环的输出频率能够连续覆盖26~41 GHz。输出频率为26 GHz时,相位噪声为-103 dBc/Hz@10 MHz,功耗为34.64 mW。输出频率为41 GHz时,相位噪声为-96 dBc/Hz@10 MHz,功耗为35.44 mW。

A 26~41 GHz Phase-Locked Loop with Adaptive Frequency Calibration Cell

A 26~41 GHz phase-locked loop (PLL) with adaptive frequency calibration was designed in a 45 nm SOI CMOS process. The loop included an input buffer, a phase-frequency detector, a charge pump, a loop filter, a voltage controlled oscillator, a MUX buffer, a divider and a digital calibration unit. An integer frequency division PLL architecture was adopted on the basis of dual LC-VCOs with an adaptive frequency selection digital calibration algorithm, so that the designed PLL could adjust the operating frequency according to the reference clock automatically. Simulation results showed that the PLL could achieve continuous coverage of output frequency range from 26 GHz to 41 GHz. The phase noise was -103 dBc/Hz@10 MHz and the power consumption was 34.64 mW when the output frequency was 26 GHz. At 41 GHz output frequency, the phase noise was -96 dBc/Hz@10 MHz and the power consumption was 35.44 mW.