| 基于UVM的AXI总线验证IP设计 |
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| 引用本文： | 刘达,倪伟,徐春琳. 基于UVM的AXI总线验证IP设计[J]. 微电子学, 2019, 49(5): 680-685 |
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| 作者姓名： | 刘达 倪伟 徐春琳 |
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| 作者单位： | 合肥工业大学 微电子设计研究所, 合肥 230601,合肥工业大学 微电子设计研究所, 合肥 230601,合肥工业大学 微电子设计研究所, 合肥 230601 |
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| 摘 要： | 基于UVM技术设计了可用于验证AXI总线协议的验证IP,对支持AXI4接口的Block RAM IP进行了验证,并构建了多Master和多Slave互联模拟验证平台,验证多AXI设备互联场景。设计了三种类型的测试用例(随机测试、基础测试和错误测试),并通过统计功能覆盖率来评估验证的完整性。验证结果表明,该验证IP功能正确,可满足对AXI总线的验证要求,功能覆盖率达到100%。
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| 关 键 词： | UVM AXI协议 验证IP |
| 收稿时间： | 2018-11-13 |
Design of a UVM-Based AXI Protocol Verification IP |
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| LIU D,NI Wei and XU Chunlin. Design of a UVM-Based AXI Protocol Verification IP[J]. Microelectronics, 2019, 49(5): 680-685 |
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| Authors: | LIU D NI Wei XU Chunlin |
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| Affiliation: | Institute of VLSI Design, Hefei University of Technology, Hefei 230601, P. R. China,Institute of VLSI Design, Hefei University of Technology, Hefei 230601, P. R. China and Institute of VLSI Design, Hefei University of Technology, Hefei 230601, P. R. China |
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| Abstract: | A verification IP targeting to verify AXI protocol was developed based on UVM technology, and then was used to verify a Block RAM IP featuring AXI4 Interface. A simulation verification platform with multi-master and multi-slave interconnections was also built to verify the interconnected multiple AXI devices. Three test cases, random test, base test and error test, were designed to assess the integrity of verification by measuring the function coverages. The simulation results showed that the functionality of the designed verification IP was correct, and the ratio of the function coverage reached 100%. |
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