基于JESD204B协议的并行加解扰电路

针对串行加解扰电路存在功耗大、数据处理速度慢、串行扰码需要较高时钟频率等问题,提出了一种基于JESD204B协议的新型并行加解扰电路,通过由矩阵推导出的算法实现32位数据并行加扰/解扰。使用Verilog HDL对电路进行RTL级设计,并通过Cadence公司的NCVerilog软件进行验证。结果表明,该电路能够正确实现加解扰功能,并且可以使用312.5 MHz的时钟处理10 Gb/s的数据。采用65 nm CMOS工艺制作样片,测试结果表明,该电路符合设计要求。该加解扰电路对于高速数据通信芯片的自主可控设计与实现具有重要的参考价值。

A Parallel Scrambling and Descrambling Circuit Based on JESD204B Protocol

There are problems in the serial scrambling and descrambling circuit, such as large power consumption, slow data processing speed, and high clock rate requirement. For these problems, a design scheme of a novel parallel scrambling and descrambling circuit based on JESD204B protocol was proposed, which implemented 32-bit data parallel operations of scrambling/descrambling through an algorithm derived from matrices. The circuit was designed at RTL level by Verilog HDL, and verified by Cadence''s NCVerilog software. The results showed that the circuit could correctly implement the function of scrambling/descrambling, and could process 10 Gb/s data with a 312.5 MHz clock. The sample circuit was fabricated in a 65 nm CMOS process, and the test results showed that the circuit had met the design requirements. The proposed circuit had an important reference significance for the independent and controllable design and implementation of high speed data communication chips.