| 高性能连续时间Sigma-Delta调制器系统级设计 |
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| 引用本文： | 褚子乔,王东辉,侯朝焕. 高性能连续时间Sigma-Delta调制器系统级设计[J]. 微电子学与计算机, 2008, 25(8) |
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| 作者姓名： | 褚子乔 王东辉 侯朝焕 |
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| 作者单位： | 中国科学院,声学研究所,北京,100080 |
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| 摘 要： | 介绍了高性能连续时间Sigma-Delta调制器的系统设计和行为级建模的方法,并通过在噪声整形滤波器中加入一对零点改善了调制器带内信噪比.仿真结果显示,该调制器适用于转换精度14位,转换速率7.8Msps的多bit连续时间Sigma-Delta A/D转换器.
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| 关 键 词： | Sigma-Delta调制器 过采样 连续时间 多bit量化 |
Architecture Design of a High Resolution Continuous-Time Sigma-Delta Modulator |
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| CHU Zi-qiao,WANG Dong-hui,HOU Chao-huan. Architecture Design of a High Resolution Continuous-Time Sigma-Delta Modulator[J]. Microelectronics & Computer, 2008, 25(8) |
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| Authors: | CHU Zi-qiao WANG Dong-hui HOU Chao-huan |
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| Abstract: | Illuminated by a real design case,an architecture design method of high resolution multi-bit continuous-time Sigma-Delta modulator is presented.A test-bench for the further circuit design is also introduced.Simulation results show that the modulator achieves a 14bits and 7.8Msps resolution. |
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| Keywords: | Sigma-Delta modulator over-sampling continuous-time multi-bit |
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