多芯片叠层封装中的芯片应力分析及结构优化

针对典型的四层芯片叠层封装产品,采用正交试验设计与有限元分析相结合的方法研究了芯片、粘合剂、顶层芯片钝化层和密封剂等十个封装组件的厚度变化对芯片上最大热应力的影响,并利用找到的主要影响因子对封装结构进行优化.结果表明,该封装产品可以在更低的封装高度下实现,并具有更低的芯片热应力水平及更小的封装体翘曲,这有助于提高多芯片叠层封装产品的可靠性.

Chip Stress Analysis and Structure Optimization in Stacked Multi-Chip Package

Finite element analysis and design of experiments are adopted to systematically investigate the influence of component thicknesses on maximum thermal stress of die for a typical stacked four-chip package (MCP) structure. These components include all layers involved in MCP structure such as dies,die attaches,mould compound,and top die passivation. Structure optimization of the package design in different approaches shows that thinner package body,lower chip stress level and smaller package warpage can be realized in this product. The study would be beneficial to improve the reliability of stacked MCP products.