| 基于CMOS多功能数字芯片的ESD保护电路设计 |
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| 引用本文： | 周子昂,姚遥,徐坤,张利红.基于CMOS多功能数字芯片的ESD保护电路设计[J].电子科技,2012,25(4):57-59. |
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| 作者姓名： | 周子昂 姚遥 徐坤 张利红 |
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| 作者单位： | (周口师范学院 物理与电子工程系,河南 周口 466001) |
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| 基金项目： | 周口师范学院青年科研基金资助项目 |
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| 摘 要： | 基于CSMC 2P2M 0.6 μm CMOS工艺设计了一种ESD保护电路。整体电路采用Hspice和CSMC 2P2M 的0.6 μm CMOS工艺的工艺库(06mixddct02v24)仿真,基于CSMC 2P2M 0.6 μm CMOS工艺完成版图设计,并在一款多功能数字芯片上使用,版图面积为1 mm×1 mm,参与MPW(多项目晶圆)计划流片,流片测试结果表明,芯片满足设计目标。
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| 关 键 词： | CMOS工艺 ESD保护电路 版图设计 |
A Design of ESD Protection Circuit for Multi-functional Digital Chip in CMOS Process |
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| ZHOU Ziang,YAO Yao,XU Kun,ZHANG Lihong.A Design of ESD Protection Circuit for Multi-functional Digital Chip in CMOS Process[J].Electronic Science and Technology,2012,25(4):57-59. |
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| Authors: | ZHOU Ziang YAO Yao XU Kun ZHANG Lihong |
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| Affiliation: | (Department of Physics and Electronics Engineering,Zhoukou Normal University,Zhoukou 466001,China) |
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| Abstract: | An ESD protection circuit is designed based on CSMC 2P2M 0.6 μm CMOS process.The circuit is simulated using Hspice and the process of the CSMC 2P2M 0.6 μm CMOS(06 mixddct02v24),the layout is based on CSMC 2P2M 0.6 μm CMOS and is used in a Multi-functional Digital Chip.The chip area is 1 mm×1 mm.The design has been successfully implemented by participating in the plan of the Multi Project Wafer.Measurements indicate that the wafer achieves the expected goals. |
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| Keywords: | CMOS Process ESD protection circuit layout design |
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