| 基于Cadence的源同步时序仿真 |
| |
| 引用本文： | 朴卫杰,程号. 基于Cadence的源同步时序仿真[J]. 电子科技, 2012, 25(5): 38-40,43 |
| |
| 作者姓名： | 朴卫杰 程号 |
| |
| 作者单位： | (西安电子科技大学 电子工程学院,陕西 西安 710071) |
| |
| 摘 要： | 根据源同步的一些基本问题,在Cadence仿真环境下,对源同步时序进行仿真,仿真结果表明,设计能满足噪声容限和过冲,仿真后的可知数据线和时间的延时约为0.3 ns,满足源同步系统设计要求。
|
| 关 键 词： | 信号完整性 源同步时序 Cadence |
Source Synchronous Timing Simulation Based on the Cadence |
| |
| PIAO Weijie,CHENG Hao. Source Synchronous Timing Simulation Based on the Cadence[J]. Electronic Science and Technology, 2012, 25(5): 38-40,43 |
| |
| Authors: | PIAO Weijie CHENG Hao |
| |
| Affiliation: | (School of Electric Engineering,Xidian University,Xi'an 710071,China) |
| |
| Abstract: | As the clock frequency becoming more and more high,the PCB design has become more and more complex,and signal Integrity simulation becomes more and more important.In this paper,according to the source synchronization of some basic issues in the Cadence simulation environment,simulate the source synchronous timing,and get simulation process and results. |
| |
| Keywords: | SI source synchronous timing Cadence |
| 本文献已被 CNKI 维普 万方数据 等数据库收录！ |
| 点击此处可从《电子科技》浏览原始摘要信息 |
|
点击此处可从《电子科技》下载全文 |
|
