| 一种基于FPGA的慢门限恒虚警处理电路设计 |
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| 引用本文： | 薛萍冰.一种基于FPGA的慢门限恒虚警处理电路设计[J].电子科技,2012,25(5):64-65,93. |
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| 作者姓名： | 薛萍冰 |
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| 作者单位： | (中国电子科技集团公司第38研究所 数字技术部,安徽 合肥 230088) |
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| 摘 要： | 雷达信号的检测多是在干扰背景下进行,如何从干扰中提取目标信号,不仅要求有一定的信噪比,而且必需有恒虚警处理设备。恒虚警处理是雷达信号处理的重要组成部分,慢门限恒虚警处理主要是针对接收机热噪声,文中介绍一种基于FPGA嵌入式设计的慢门限恒虚警处理电路,给出了仿真模型及仿真结果,并已将其用于某检测器中,取得了良好的经济效益。
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| 关 键 词： | 慢门限 恒虚警处理 FPGA |
A Design of Slow-threshold Constant False Alarm Processing Circuit Based on FPGA |
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| XUE Pingbing.A Design of Slow-threshold Constant False Alarm Processing Circuit Based on FPGA[J].Electronic Science and Technology,2012,25(5):64-65,93. |
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| Authors: | XUE Pingbing |
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| Affiliation: | (Digital Technology Division,No.38 Institution of CETC,Hefei 230088,China) |
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| Abstract: | The detection of radar signal always processes with background noise,not only high signal noise ratio but also constant false alarm device are required to reduce constant false alarm.Constant false alarm processing is an important part of radar signal processing;therefore the research on false alarm processing is crucial in radar technology.Slow-threshold constant false alarm aim at the heat noise of receiver,a constant false alarm processing circuit based on FPGA embedded design is proposed in this paper,and the simulation model and simulating results are also presented.The circuit has been used in a practical detector with big economic benefit. |
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| Keywords: | slow-threshold constant false alarm processing FPGA |
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