基于小数分频的锁相环设计

锁相环电路广泛应用于现阶段集成电路芯片中,由于需要较高的输出频率解析度,小数分频的锁相环得到了越来越多的关注。但是小数分频调制器会引入较大的噪声,因此如何降低系统噪声、提供高性能相位噪声的锁相环成为现阶段研究的重要课题。文章给出了基于小数分频技术的锁相环设计与噪声分析,分析了各个主要模块的设计要求与优化方法。芯片在SMIC流片制造,采用了0.13μm逻辑工艺,从样片的测试结果来看,Sigma-Delta模块的噪声得到了较好的抑制,满足了预先的设计要求。

Fraction-N Phase-locked Loop Design

Phase-locked loop is widely used in SOC solutions. Because of the high output frequency resolution required, fraction-N phase-locked loop will be more and more popular. On the other hand, sigma-delta modulator introduce noise to the phase-locked loop, which decrease the phase-locked loop phase noise performance. This paper present a fraction-N phase-locked loop, which used sigma-delta modulator as the fraction-N divider, it gives the phase noise analysis for each building block, then give the loop optimize methodology to improve the performance. This chip is fabricated by SMIC 0.13μm logic process, the output resolution achieved 1Hz, and the phase noise performance is -123dB@1MHz.