Short-channel-effect-suppressed sub-0.1-μm grooved-gate MOSFET'swith W gate |
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Authors: | Kimura S Tanaka J Noda H Toyabe T Ihara S |
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Affiliation: | Central Res. Lab., Hitachi Ltd., Tokyo; |
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Abstract: | Grooved-gate Si MOSFET's with tungsten gates are fabricated using conventional manufacturing technologies, and their short-channel-effect-free characteristics are verified down to a source and drain separation of around 0.1 μm. Phase shift lithography followed by a side-wall oxide film formation technique achieves a spacing of less than 0.2 μm between adjacent elevated polysilicons, subsequently resulting in a sub-0.1-μm source and drain separation in the substrate. Short-channel effects, such as threshold voltage roll-off and punchthrough, are found to be completely suppressed. From device simulations, the potential barrier formed at each grooved-gate corner is considered to be responsible for the suppression of the short-channel effects |
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