Instruction Set Extensions for MPEG-4 Video |
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Authors: | Mladen Berekovic Hans-Joachim Stolberg Mark B Kulaczewski Peter Pirsch Henning Möller Holger Runge Johannes Kneip and Benno Stabernack |
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Affiliation: | (1) Laboratorium für Informationstechnologie, Universität Hannover, Germany;(2) Robert Bosch GmbH, Hildesheim, Germany;(3) Heinrich-Hertz-Institut, Berlin, Germany |
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Abstract: | This paper describes instruction set extensions for the acceleration of MPEG-4 algorithms on programmable (RISC-) CPUs. MPEG-4 standardizes audio and video compression schemes for a variety of bit rates and scenarios. As MPEG-4 targets a much broader range of different applications than previously defined hybrid video coding standards like H.263 or MPEG-2, it employs a much higher number of different algorithms and coding modes. Therefore, MPEG-4 implementations will require a more software-oriented approach to be efficient. However, the total computational load for an optimized implementation of an MPEG-4 video codec is expected to exceed the performance levels of today's multimedia signal processors, making further hardware acceleration a necessity. For that purpose, we propose a number of instruction set extensions that add function-specific blocks to the data path of a CPU. These dedicated modules are highly adapted to the most computation-intensive processing schemes of MPEG-4, such as DCT, motion compensation, padding, shape coding, or bitstream parsing. The increased functionality of basic instructions results in a significant speed-up over standard RISC instruction sets, thus making MPEG-4 implementations feasible on programmable processor platforms. Possible target architectures include VLIW multimedia processors, MIMD-style multiprocessors, or coprocessor architectures |
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