Design of the CMOS low power sub-sampler with integrated filtering for the internet of things

To solve cost and power consumption problems of wireless communication of the internet of things (IoT), a CMOS low power sub-sampler with filtering is proposed. Based on the subsampling theory, the sub-sampler adopts the clock signal with the high sampling ratio to achieve the passive subsampling mixer. It incorporates the sampling switches and capacitors directly into the parallel resonant output load of the balun low noise amplifier (balun-LNA) to form the bandpass filter, which reduces noise folding to improve the noise figure. And with the integrated balun-LNA instead of the off-chip balun it generates the differential signal, which achieves high integration and low power consumption of the system. For the application of IoT wireless communication, the sub-sampler is implemented and simulated based in the UMC 65nm CMOS process. The results show that it can achieve the subsampling frequency down-conversion at the sensitivity of -90dBm by using the clock sampling frequency of 41MHz operating at the central frequency of 780MHz, which acquires a high sampling ratio and better out-band rejection, and its current consumption is 1.6mA at the 1.2V voltage supply. In addition, the proposed sub-sampler chooses the proper sampling frequency to achieve the frequency conversion flexibly, based on different RF signal frequencies.