纳米级CMOS集成电路的单粒子效应及其加固技术

空间应用的集成电路受到辐射效应的影响,会出现瞬态干扰、数据翻转、性能退化、功能失效甚至彻底毁坏等问题.随着器件特征尺寸进入到100nm以下（以下简称纳米级）,这些问题的多样性和复杂性进一步增加,单粒子效应成为集成电路在空间可靠性应用的主要问题,给集成电路的辐射效应评估和抗辐射加固带来了诸多挑战.本文以纳米级CMOS集成电路为研究对象,结合近年来国内外的主要技术进展,介绍研究团队在65nm集成电路单粒子效应和加固技术方面的研究成果,包括首次提出的单粒子时域测试和分析方法、单粒子多节点翻转加固方法和单粒子瞬态加固方法等.

Single Event Effect and its Hardening Technique in Nano-scale CMOS Integrated Circuits

The integrated circuits used in aerospace can be influenced by space radiation effects,leading to some problems such as transient disturbance,data upset,performance degradation,functional failure or even destructive damage.The variety and complexity of these problems increases as the feature size of devices scales down to less than 100 nm (called as "nano-scale" in this paper).Single event effect has become a main reliability factor for space-used ICs,and brought about much challenge to radiation hardness assurance and radiation hardening.Taking nano-scale ICs as the research object,combined with recent technology progress,this paper introduces the research achievements in single event effect and hardening techniques of 65 nm ICs,including the proposed time-domain testing and analyzing method,radiation hardening techniques for single event multi-node upsets and single event transients.