| 基于FPGA 的SRIO 端点设计与实现 |
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| 引用本文： | 陈,刚.基于FPGA 的SRIO 端点设计与实现[J].兵工自动化,2021,40(2):49-52. |
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| 作者姓名： | 陈 刚 |
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| 作者单位： | 中国兵器装备集团自动化研究所有限公司特种计算机事业部,四川 绵阳 621000;陆军装备部驻重庆地区代表局驻广元地区军代室,四川 广元 628017 |
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| 摘 要： | 为提高芯片间及板间互连的带宽、灵活性和可靠性,提出一种基于FPGA(field programmable gate array)的SRIO(serial rapid IO)端点的设计方法.介绍RapidIO的应用,对SRIO IP核及其参数设置进行分析,结合Xilinx提供的官方例程,编写用户逻辑,完成FPGA与DSP的高速通信,测试结果表明:该设计具有较高的带宽,有一定的参考价值.
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| 关 键 词： | 嵌入式系统 赛灵思 高速通信 |
| 收稿时间： | 2020/9/21 0:00:00 |
| 修稿时间： | 2020/10/24 0:00:00 |
Design and Implementation of SRIO Endpoint Based on FPGA |
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| Chen Gang,Kang Lin,Chen Hang,Li Kunhe.Design and Implementation of SRIO Endpoint Based on FPGA[J].Ordnance Industry Automation,2021,40(2):49-52. |
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| Authors: | Chen Gang Kang Lin Chen Hang Li Kunhe |
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| Abstract: | In order to improve the bandwidth, flexibility and reliability of inter chip and inter board interconnection,
this paper proposes a design method of SRIO (serial rapid IO) endpoint based on field programmable gate array (FPGA).
Introduces the application of RapidIO, analyzes the SRIO IP core and its parameter setting, compiles the user logic with the
official example provided by Xilinx, and realizes the high-speed communication between FPGA and DSP. The test results
show that the design has a high bandwidth and a certain reference value. |
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| Keywords: | embedded system Xilinx high-speed communication |
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