| 高速模数转换器时钟的设计与仿真 |
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| 引用本文： | 李楠,吴建飞,步凯.高速模数转换器时钟的设计与仿真[J].现代仪器,2007,13(5):49-51,58. |
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| 作者姓名： | 李楠 吴建飞 步凯 |
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| 作者单位： | 国防科技大学电子科学与工程学院,长沙,410073 |
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| 摘 要： | 介绍一种应用于高速模数转换器中的交流耦合形式的PECL时钟设计方法。在时钟的端接设计中,采用串联终端匹配改善信号完整性,并利用HyperLynx软件进行仿真,取得良好的效果,对于实际电路设计有良好的指导作用。
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| 关 键 词： | 高速模数转换器 PECL时钟 Hyperlynx |
Clock design and simulation in high-speed ADC |
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| Li Nan,Wu Jianfei,Bu Kai.Clock design and simulation in high-speed ADC[J].Modern Instruments,2007,13(5):49-51,58. |
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| Authors: | Li Nan Wu Jianfei Bu Kai |
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| Affiliation: | National University of Defense Technology, College of Electronic Science and Engineering, Changsha 410073 |
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| Abstract: | A design method of AC-coupling PECL clock of high-speed ADC is introduced. Series termination was applied in the design of termination schemes in order to improve signal integrity. By using HyperLynx simulation software, the good performance achieved, and making practical circuit design more easy. |
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| Keywords: | Hyperlynx |
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