一种行为级可测试性综合方法

伴随着高层次综合技术的普及和深入，高层次可测试性综合技术引起了广泛的关注。在简单介绍当前可测试性综合技术的现状后，提出了采用“VHDL进，VHDL出”的方式进行行为级可测试性综合的流程，并提出了一个新的行为级可测试性分析算法，然后讨论了测试点的选择、可测试结构的规范化描述和自动插入的技术与方法。

Synthesis for Testability of Non-Separable Controller Datapath Circuits from Behavioral Descriptions

By the development and popularization of high-level synthesis technology,the synthesis method for testability becomes more and more important.In this paper,a new method is proposed to implement the synthesis, which introduces the flow of VHDL-in and VHDL-out.A new behavioral testability analysis algorithm is presented which is one of the key techniques of synthesis for testability.According to the testability analysis result,test points are selected and test behavior is inserted.The normal-mode design behavior and test-mode test behavior are combined and then can be synthesized by any general-purpose synthesis system to produce a testable circuit.