A 2.5-V, 72-Mbit, 2.0-GByte/s packet-based DRAM with a 1.0-Gbps/pininterface |
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| Authors: | Kim C Kyung K-H Jeong W-P Kim J-S Moon B-S Chai J-W Yim S-M Choi J-H Han K-H Park C-J Hwang H-S Choi H Cho S-B Portmann L Cho S-I |
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| Affiliation: | Samsung Electron. Co. Ltd., Yongin City; |
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| Abstract: | A 2.5-V, 72-Mbit DRAM based on packet protocol has been developed using (1) a rotated hierarchical I/O architecture to reduce power noise and to minimize the chip-size penalty associated with an 8-bit prefetch architecture implemented with 16 internal banks and 144 I/O lines, (2) a delay-locked-loop circuit using a high-speed and small-swing differential clock to achieve the peak bandwidth of 2.0 GByte/s in a single chip with low noise sensitivity, and (3) a flexible column redundancy scheme to efficiently increase redundancy coverage using a shifted I/O line scheme for multibank architecture |
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