Analysis and impact of process variability on performance of junctionless double gate VeSFET |
| |
Authors: | TChaudhary GKhanna |
| |
Affiliation: | National Institute of Technology, Hamirpur 177005, Himachal Pradesh, India |
| |
Abstract: | This paper presents an in-depth analysis of junctionless double gate vertical slit FET (JLDG VeSFET) device under process variability. It has been observed that junctionless FETs (JLDG VeSFET) are significantly less sensitive to many process parameter variations due to their inherent device structure and geometric properties. Sensitivity analysis reveals that the slit width, oxide thickness, radius of the device, gate length and channel doping concentration imperceptibly affect the device performance of JLDG VeSFET in terms of variation in threshold voltage, on current, off current and subthreshold slope (Ssub) as compared to its junction based counterpart i.e. MOSFET, because various short channel effects are well controlled in this device. The maximum variation in off current for JLDG VeSFET due to variation in different devices parameters is 5.6% whereas this variation is 38.8% for the MOS junction based device. However, variation in doping concentration in the channel region displays a small deviation in the threshold voltage and on current characteristics of the MOSFET device as compared to JL DG VeSFET. |
| |
Keywords: | JLDG VeSFET process variation sensitivity scaling short channel effects oxide thickness channel thickness threshold voltage |
本文献已被 万方数据 等数据库收录! |
| 点击此处可从《半导体学报》浏览原始摘要信息 |
|
点击此处可从《半导体学报》下载全文 |
|