| 多路百兆比以太网接口卡的研制 |
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| 引用本文： | 马军,尹华锐,徐佩霞. 多路百兆比以太网接口卡的研制[J]. 数据采集与处理, 2002, 17(4): 428-432 |
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| 作者姓名： | 马军 尹华锐 徐佩霞 |
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| 作者单位： | 中国科学技术大学电子工程与信息科学系,合肥,230027 |
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| 基金项目： | 国家 8 6 3计划 (编号 :86 3-31 7-0 1 -99)资助项目 |
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| 摘 要： | 介绍了一种用于边缘路由器的多路百兆比以大网卡的系统硬件结构和软件实现。该卡利用两片超大规模高速FPGA芯片，同时处理六路全双工百兆比以大网数据的发送和接收，六路数据完全独立。为实现这种多路高速数据之间的独立以及实时、无差错、高质量传输，本文通过硬件体系结构和逻辑设计的方法，给出了这种高速高质量宽带多业务接入的复用解复用算法的实现策略。
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| 关 键 词： | 多路百兆比以太网接口卡 路由器 数据传输 边缘路由器 Internet 接人系统 |
| 文章编号： | 1004-9037(2002)04-0428-05 |
| 修稿时间： | 2001-10-20 |
Development of Multi-Channel Fast Ethernet Access Card |
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| Ma Jun Yin Huarui Xu Peixia. Development of Multi-Channel Fast Ethernet Access Card[J]. Journal of Data Acquisition & Processing, 2002, 17(4): 428-432 |
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| Authors: | Ma Jun Yin Huarui Xu Peixia |
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| Affiliation: | Ma Jun Yin Huarui Xu Peixia Department of Electronic Engineering and Information Science,University of Science and Technology of China Hefei 230027,P.R.China |
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| Abstract: | The system hardware architecture and the software implementation of the multiple 100M-Ethernet network-card used in the edge router are described. The multiplex-and-de-multiplex algorithm is used for the efficient broadband multi-service accessing with 2 VLSI high-speed FPGA chips. The data transmission from different channels is real-time,errorless,and high-quality. Experimental results indicate that it allows high quality multiplexing and de-multiplexing for 6 routes of 100M-Ethernet data with hardware structure design and logic program. |
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| Keywords: | multichannel broadband access multiplex field programmable gate array (FPGA) |
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