| 缓冲区结构效率分析 |
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| 引用本文： | 苏航,薛彦涛.缓冲区结构效率分析[J].计算机工程,2011,37(13):20-25. |
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| 作者姓名： | 苏航 薛彦涛 |
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| 作者单位： | 1. 兰州大学信息科学与工程学院,兰州,730000
2. 中国肮天二院研究生院,北京,100854 |
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| 摘 要： | I/O设备与CPU的速度不匹配，制约了计算机系统性能的进一步提高。为此，根据计算机体系结构，对缓冲区结构的效率进行分析，使用EDA计算机辅助设计软件QuartusII设计异步双时钟FIFO缓冲区，并对其进行仿真验证及数据记录，通过对数据的分析，证明系统整体效率与FIFO效率密切相关，只有实现FIFO效率的最大化，才能使系统整体效率最大化，同时FIFO效率最大化也只能在完成系统效率最大化的过程中得以实现。
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| 关 键 词： | 异步FIFO 结构效率 EDA设计 亚稳态 |
| 收稿时间： | 2011-02-01 |
Efficiency Analysis of Buffer Structure |
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| SU Hane,WE Yan-tao.Efficiency Analysis of Buffer Structure[J].Computer Engineering,2011,37(13):20-25. |
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| Authors: | SU Hane WE Yan-tao |
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| Affiliation: | 1.School of Information Science & Engineering,Lanzhou University,Lanzhou 730000,China;2.The Graduate School of The Second Academy of China Aerospace,Beijing 100854,China) |
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| Abstract: | To solve the problem of the data transmission speed mismatch between I/O device and CPU,this paper analyzes the efficiency of various buffer structure based on computer architecture.With QuartusII which is Computer-Aided Design（CAD） using Electronic Design Automation（EDA） software,it designs the asynchronous dual-clock First In First Out（FIFO） buffer,including the buffer structure of the simulation,data recording,and analysis of its effectiveness.Analysis results show that the efficiency of computer system is closely related with that of FIFO.To improve the efficiency of computer system,the efficiency of FIFO is supposed to be improved first.At the same time,the improvement of the efficiency of FIFO is based on the improvement of the efficiency of computer system |
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| Keywords: | asynchronous First In First Out（FIFO） structure efficiency Electronic Design Automation（EDA） design metastable state |
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