VSP中的变字长解码器设计研究

提出了视频信号处理器中的变长解码器核设计．采用基于PLA的并行算法，在PLA中存储了以编码码字为输入，码值和码长为输出的各个变长码真值表．用从PLA中查出的码长来控制桶形移位器的位移，实现每个周期解出一个码字．VLD采用了数据驱动原理，并在任务分配方面进行了调整，以适应VSP进行任务流水的总体要求．

Research on design of variable length decoder in video signal processor

The design of Variable Length Decoder core with parallel algorithm based on PLA is presented in this paper. Each Variable Length Code truth-table whose input is the bit stream code and output is the value and length of code is stored into different PLA respectively. The PLA's output code length controls the barrel shifter to eject the right number of bits from the bit stream, and one variable length code can be decoded in each clock cycle. Because the decoding time varies with different VLD streams, the decoder's control strategy is implemented with data drive principle and adjusted to balance task assignment to realize the task level pipeline required by VSP. Compared with conventional method, the proposed method in this paper is featured with high parallel processing speed and less hardware requirement by asing PLA. So it can be implemented in VLSI.