第二代数字广播电视系统前向纠错编码硬件实现研究

分析了DVB-S2中BCH码LDPC码的特点,给出了一种面向FPGA的BCH和LDPC码级联码编码器的实现方案,并采用Verilog HDL语言在Virtex 4 xc4vlx60芯片上实现了编码器的设计。设计中BCH码主要由移位寄存器构成,LDPC码则采用多个B10ckRAM存储校验位,实现了与同一信息位关联的所有校验位的并行处理,提高了编码速度。综合结果表明:该编码器的吞吐量约为64.30 Mb/s,在占用资源较少的情况下满足了DVB-S2标准的要求。

FPGA implementation of FEC encoder in DVB-S2

This paper analyses the characteristic of BCH codes and LDPC codes in DVB-S2, and proposes an encoding architecture for FPGA implemented with Verilog HDL language on the chip of Virtex 4 xc4vlx60. The design method adopts many BlockRAMs to process all the parity bits relating to the same information bit in parallel, thus improve the encoding speed. Synthesis results show that this encoder has a throughput about 49.95 Mb/s, and satisfies the demand of DVB-S2 at the cost of low resource occupation.