一种基于FPGA的容错嵌入式系统设计

在FPGA内部使用各种IP软核搭建了完整的嵌入式系统，实现了用三个MicroBlaze CPU软核进行表决的三模冗余容错方案。同时对μC／OS—Ⅱ操作系统以及应用程序进行改进，在程序的内部加入了错误检测和校正(EDAC)、函数堆栈保护等容错功能。通过实验证明，该系统减小了器件本身和内存模块受到的SEU(Single Event Upset)影响。

Design of a FPGA-based fault-tolerant embedded system

Using all kinds of soft IP cores, a complete embedded system was set up in the FPGA. Due to the flexibility of FPGA design, the TMR of the three MicroBlaze soft cpu cores and a voter was implemented on the FPGA. At the same time,the support of software fault tolerance by the way of the EDAC(Error Detection And Correction) and the protection of system stack were added. The experiment results show that the system is equipped with the ability of the tolerance of the effect caused by SEU(Single Event Upset).