一种0.6 V低压两级时间数字转换器

研究了用于超低功耗全数字锁相环(ADPLL)的时间数字转换器(TDC)在近阈值电源电压下的工作原理,提出了一种近阈值电压时间转换器。采用两级量化的TDC,通过时间放大器对量化余量进行放大,实现二次量化。针对TDC低压下的功耗、速度问题,实现了一种增益可扩展的时间放大器,提高了时间分辨率。基于130 nm CMOS工艺的仿真结果表明,两级量化时间数字转换器的分辨率为2.5 ps,动态范围为640 ps,微分非线性(DNL)最大值为0.9 LSB,积分非线性(INL)最大值为2.3 LSB。4倍时间放大器的增益误差为8.2%。

A 0.6 V Low Voltage Time-to-Digital Converter with Two Stage Structure

Time to digital converter (TDC) is the key module of ultra-low power all digital phase locked loop (ADPLL). The principle of TDC under the near threshold power voltage was investigated, and a near threshold voltage time converter circuit was introduced. The two stage quantized TDC structure and time amplification was adopted in the circuit, which could enlarge the quantization margin and realize the second quantization. To solve the problem of power consumption and speed of TDC in low voltage, a gain scalable time amplifier was implemented to improve the time resolution of TDC. The TDC was simulated in a 130 nm CMOS process. The simulation results indicated that the optimized TDC could realize a resolution of 2.5 ps. The dynamic range was 640 ps, the maximum value of differential non-linearity (DNL) was 0.9 LSB, and the maximum value of integral non-linearity (INL) was 2.3 LSB. The gain error of quadruple time amplifier was 8.2%.