A 5-GHz CMOS double-quadrature receiver front-end with single-stage quadrature generator |
| |
| Authors: | Chung-Yu Wu Chung-Yun Chou |
| |
| Affiliation: | Inst. of Electron., Nat. Chiao Tung Univ., Hsinchu, Taiwan; |
| |
| Abstract: | A 5-GHz CMOS double-quadrature front-end receiver for wireless LAN application is proposed. In the receiver, a one-stage RLC phase shifter is used to generate quadrature RF signals. Implemented in 0.18 /spl mu/m CMOS technology, the receiver chip can achieve 50.6-dB image rejection with power dissipation of 22.4 mW at 1.8-V voltage supply. |
| |
| Keywords: | |
|
|
