Effects of GaAs buffer layer and lattice-matching on deep levels in Zn(S)Se/GaAs heterostructures |
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Authors: | Mitsuru Funato Hiroaki Kitani Shizuo Fujita Shigeo Fujita |
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Affiliation: | (1) Department of Electronic Science and Engineering, Kyoto University, 606-01 Kyoto, Japan |
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Abstract: | The effects of GaAs buffer layer and lattice-matching on the nature of deep levels involved in Zn(S)Se/GaAs heterostructures are investigated by means of deeplevel transient spectroscopy (DLTS). The heterojunction diodes (HDs) where nZn(S)Se is grown on p+-GaAs by metalorganic vapor phase epitaxy are used as a test structure. The DLTS measurement reveals that when ZnSe is directly grown on a GaAs substrate, there exist five electron traps A-E at activation energies of 0.20, 0.23, 0.25, 0.37, and 0.53 eV, respectively. Either GaAs buffer layer and lattice-matching may reduce the incorporation of traps C, D, and E, implying that these traps are ascribed to surface treatment of GaAs substrate and to lattice relaxation. Concentration of trap B, which is the most dominant level, is proportional to the donor concentration. However, in the ZnSSe/GaAs sub. HD, another trap level, instead of trap B, locates at the almost same position as that of trap B, and it shows anomalous behavior that the DLTS peak amplitude changes drastically as changing the rate windows. This is explained by the defect generation through the interaction between sulfide and a GaAs substrate surface. For the trap A, the concentration is a function of donor concentration and lattice mismatch, and the origin is attributed to a complex of donor induced defects and dislocations. |
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Keywords: | DLTS GaAs buffer layer lattice-matching ZnSe Zn(S)Se/GaAs heterostructure |
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