| 基于CPLD的C8051F单片机高速数据采集系统设计 |
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| 引用本文： | 陈宇,张跃飞,陈保立. 基于CPLD的C8051F单片机高速数据采集系统设计[J]. 光电技术应用, 2012, 27(5): 5-9 |
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| 作者姓名： | 陈宇 张跃飞 陈保立 |
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| 作者单位： | 1. 中北大学机电工程学院,山西 太原 030051
2. 中北大学信息与通信工程学院,山西 太原 030051 |
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| 基金项目： | 山西省回国留学人员重点科研资助项目(2008003) |
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| 摘 要： | 设计了以CPLD为采集控制单元的高速数据采集系统。此系统采用CPLD对串行AD和串行铁电存储器的进行时序控制,协助芯片单片机C8051F020进行逻辑控制和时序协调。系统可实现采样频率2 MHz、采样精度12-bits、体积小和功耗低。该设计已经成功应用在测试中,其性能和指标均优于应用要求。
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| 关 键 词： | 数据采集 串行 CPLD 时序 控制 |
| 收稿时间： | 2012-07-23 |
Design of C8051F High-speed Data Acquisition System Based on CPLD |
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| CHEN Yu,ZHANG Yue-fei,CHEN Bao-li. Design of C8051F High-speed Data Acquisition System Based on CPLD[J]. Electro-Optic Technology Application, 2012, 27(5): 5-9 |
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| Authors: | CHEN Yu ZHANG Yue-fei CHEN Bao-li |
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| Affiliation: | 1.Mechanics and Electricity Engineering College,North University of China,Taiyuan 030051,China;2.Information and Communication Engineering College,North University of China,Taiyuan 030051,China) |
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| Abstract: | A high-speed data acquisition system using CPLD as an acquisition control unit is designed. CPLD is used to control the time sequence of serial AD and serial ferroelectric memory in the system. And CPLD is helpful to perform logic control and time sequence coordination on single chip C8051F020. The system has the characteristics of 2 MHZ sampling frequency, 12-bits sampling precision, small volume and low power dissipation. The design is applied in experimental test successfully and its performance and indexes are both better than application requirements. |
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| Keywords: | data acquisition serial CPLD time sequence control |
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