3.5-Gb/s×4-ch Si bipolar LSI's for optical interconnections |
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Authors: | Ishihara N Fujita S Togashi M Hino S Arai Y Tanaka N Kobayaski Y Akazawa Y |
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Affiliation: | NTT LSI Labs., Atsugi; |
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Abstract: | The 3.5-Gb/s, 4-ch transmitter and receiver LSI's described here include a 5-to-1 multiplexer, a 1-to-5 demultiplexer, and analog PLL circuits that can generate high-speed clock (3.5 GHz) and retimed data. The chips make it possible to connect twenty pairs of 700-Mb/s electrical ports (14-Gb/s throughput) without any external elements even for the PLL. Both the transmitter and receiver LSI are 4.5-mm-square and are fabricated by a 40-GHz 0.5-μm Si bipolar process. The transmitter LSI dissipates 2.5 W, and the receiver LSI dissipates 3.6 W. Both have -4.5- and -2-V supply voltages |
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