可重构高速数据加密系统设计和实现

为解决SM4传统加解密方式存在的速度慢、效率低、占用CPU计算资源的问题,提出了一种可重构高速数据加密系统.该系统基于Xilinx Virtex UltraScale VU9p FPGA,利用PCIe热插拔特性,可快速应用于办公主机或服务器,通过PCIe高速接口实现数据的快速传输,在FPGA内实现并行可调度SM4算法逻...

Design and implementation of reconfigurable high-speed data encryption system

In order to solve the problems of slow speed, low efficiency, and CPU computing resources in the traditional SM4 encryption and decryption methods, a reconfigurable high-speed data encryption system is proposed. The system is based on Xilinx Virtex UltraScale VU9p FPGA, using PCIe hot-swappable features, can be quickly applied to office hosts or servers, fast data transmission through PCIe high-speed interface, parallel and schedulable SM4 algorithm logic in FPGA, and a dedicated DMA design The module realizes bypassing the host CPU to transmit plaintext ciphertext, reducing the resource occupation on the host side; the encryption and decryption system implemented by FPGA is reconfigurable, which greatly reduces the hardware cost of algorithm iteration. System analysis, testing and experimental results show that the system achieves high-speed and reliable data transmission and encryption, and the bus rate reaches 8GT/s, which can effectively meet the needs of fast encryption and decryption of large-capacity data; it adopts parallel schedulable pipeline encryption and decryption, which is better than traditional software. In this way, the encryption and decryption rate is increased by approximately 25.78 times.