| A 485ps 64-Bit Parallel Adder in 0.18$mu$m CMOS |
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| 引用本文： | Dong-Yu Zheng,Yan Sun,Shao-Qing Li,and Liang Fang. A 485ps 64-Bit Parallel Adder in 0.18$mu$m CMOS[J]. 计算机科学技术学报, 2007, 22(1): 25-27. DOI: 10.1007/s11390-007-9002-1 |
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| 作者姓名： | Dong-Yu Zheng Yan Sun Shao-Qing Li and Liang Fang |
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| 作者单位： | School of Computer National University of Defense Technology Changsha 410073，China，School of Computer National University of Defense Technology，Changsha 410073，China，School of Computer National University of Defense Technology，Changsha 410073，China，School of Computer National University of Defense Technology，Changsha 410073，China |
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| 基金项目： | Supported by the National Natural Science Foundation of China under Grant Nos. 60273069, 60376018, 90207011，the National High Technology Development 863 Program of China under Grant No. 2002AA110020，the Advanced Research Foundation of NUDT under Grant No. JC03-06-007. |
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| 摘 要： | This paper presents an optimized 64-bit parallel adder. Sparse-tree architecture enables low carry-merge fan-outs and inter-stage wiring complexity. Single-rail and semi-dynamic circuit improves operation speed. Simulation results show that the proposed adder can operate at 485ps with power of 25.6mW in 0.18μm CMOS process. It achieves the goal of higher speed and lower power.
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| 关 键 词： | 互补金属氧化物半导体 加法器 CMOS 计算机 |
| 收稿时间： | 2006-01-11 |
| 修稿时间： | 2006-01-112006-08-14 |
A 485ps 64-Bit Parallel Adder in 0.18μm CMOS |
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| Dong-Yu Zheng,Yan Sun,Shao-Qing Li,Liang Fang. A 485ps 64-Bit Parallel Adder in 0.18μm CMOS[J]. Journal of Computer Science and Technology, 2007, 22(1): 25-27. DOI: 10.1007/s11390-007-9002-1 |
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| Authors: | Dong-Yu Zheng Yan Sun Shao-Qing Li Liang Fang |
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| Affiliation: | School of Computer, National University of Defense Technology, Changsha 310073, China |
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| Abstract: | This paper presents an optimized 64-bit parallel adder. Sparse-tree architecture enables low carry-merge fan-outs and inter-stage wiring complexity. Single-rail and semi-dynamic circuit improves operation speed. Simulation results show that the proposed adder can operate at 485ps with power of 25.6mW in 0.18μm CMOS process. It achieves the goal of higher speed and lower power. Supported by the National Natural Science Foundation of China under Grant Nos. 60273069, 60376018, 90207011, the National High Technology Development 863 Program of China under Grant No. 2002AA110020, and the Advanced Research Foundation of NUDT under Grant No. JC03-06-007. |
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| Keywords: | parallel prefix adder semi-dynamic sparse-tree |
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